View UPD75048GC_1332489.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DATA SHEET
MOS INTEGRATED CIRCUIT
PD75048
4-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The PD75408 is a 4-bit single-chip microcomputer whose data processing capability is comparative to that of an 8-bit microcomputer. The PD75048 employs a CPU whose minimum instruction execution time is 0.95 s, and contains the EEPROM, A/D converter, multi-function timer, and high performance hardware to provide high cost to performance ratio. Detailed functions are described in the following user's manual. Read this manual when designing your system.
PD75048 User's Manual: IEU-704
FEATURES
* Built-in EEPROM: 1024 x 4 bits (data memory area) * Built-in 8-bit resolution A/D converter (successive approximation): 8 channels * Capable of operating at low voltage: VDD = 2.7 to 6.0 V * Reference voltage can be arbitrarily specified between AVREF+ and AVREF-. * Built-in multi-function timer which can provide the following functions: * 8-bit timer * PWM output * 16-bit free running timer * 16-bit integration type A/D converter counter * I/O ports: 48 pins * Middle voltage N-ch open drain input/output ports: 12 pins * 43 I/O lines can be provided with internal pulldown resistors * PROM version is available: PD75P048 (One-time PROM)
APPLICATIONS
* Consumer electronics products, telephones, cameras, automobile audio equipment, electronics measurement equipment, etc.
ORDERING INFORMATION
Part Number Package 64-pin plastic shrink DIP (750 mil) 64-pin plastic QFP ( 14mm) Quality grade Standard Standard
PD75048CW-xxx PD75048GC-xxx-AB8
Remarks: xxx is ROM code number.
Please refer to "Quality Grade on NEC Semiconductor Devices" (Document Number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
The information in this document is subject to change without notice.
Document No. IC - 2518C (O. D. No. IC - 7931C) Date Published February 1994 P Printed in Japan
The mark 5 shows major revised points.
(c) NEC Corporation 1990
PD75048
FUNCTIONAL OUTLINE
Item Instructions Instruction Execution Time Internal Memory 41
Function * With main system clock: 0.95, 1.91, 15.3 s (at 4.19 MHz) * With subsystem clock: 122 s (at 32.768 kHz) Program memory (ROM) : 8064 x 8 bits Data memory (RAM) : 512 x 4 bits Data memory (EEPROM) : 1024 x 4 bits * * * * Retains data in case of power failure Number of writes: 100,000 times Write time: 10 ms Write end, overwrite interrupt functions
EEPROM
General-Purpose Register Accumulator
* 4-bit manipulation: 8 (X, A, B, C, D, E, H, L) * 8-bit manipulation: 4 (XA, BC, DE, HL) * Bit accumulator (CY) * 4-bit accumulator (A) * 8-bit accumulator (XA) * * * * Abundant bit manipulation instructions Efficient 4-bit data manipulation instructions 8-bit data manipulation instructions GETI instruction executing 2-/3-byte instruction with a single byte 12 Input pin CMOS I/O pin (direct LED drive: 4) Medium-voltage N-ch open-drain I/O (direct LED drive) Via software, w/pull-up resistor: 27 w/pull-down resistor: 4 By mask option, w/pull-up resistor: 12
Instruction Set
I/O Line
48
24 12
* 8-bit timer/event counter * Clock source: 4 steps * Can count events * 8-bit basic interval timer * Reference time generation: 1.95, 7.82, 31.3, 250 ms (at 4.19 MHz) * Can be used as watchdog timer Timer 4 chs * Clock timer * Generates 0.5-second time intervals * Count clock source: main system clock or subsystem clock (selectable) * Clock fast forward mode (generates 3.9-ms time intervals) * Buzzer output (2, 4, 32 kHz) * Multi-function timer Can be used as: * 8-bit timer * PWM output * 16-bit free-running timer * Counter for 16-bit integral A/D converter 8-bit Serial Interface Bit Sequential Buffer Clock Output Function * Three modes: * 3-line serial I/O mode ... MSB/LSB first (selectable) * 2-line serial I/O mode * SBI mode Special bit manipulation memory: 16 bits * Ideal for remote controller Timer/event counter output (PTO0): output of square wave at specified frequency Clock output (PCL): /, fx/23 , fx/24 , fx/26 Buzzer output (BUZ): 2, 4, 32 kHz (with main system clock or subsystem clock)
2
PD75048
(cont'd)
Item A/D Converter Function 8-bit resolution A/D converter (successive approximation type): 8 channels * Low-voltage operation: VDD = 2.7 - 6.0 V * Reference voltage setting range: AVREF+ - AVREF- 2.5 V (AVREF+) - (AVREF-) 6.0 V External: 3, Internal: 6 External: 1, Internal: 1 * Ceramic/crystal oscillator circuit for main system clock oscillation * Crystal oscillator circuit for subsystem clock oscillation * STOP mode: main system clock oscillation stops * HALT mode: system clock oscillation continues (clock supply to CPU stops) * 64-pin plastic shrink DIP (750 mil) * 64-pin plastic QFP ( 14 mm)
Vector Interrupt Test Input System Clock Oscillator Circuit Standby Function Package
3
PD75048
CONTENTS 1. 2. 3. PIN CONFIGURATION (TOP VIEW) ........................................................................................ 5 BLOCK DIAGRAM ......................................................................................................................8 PIN FUNCTIONS ........................................................................................................................9
3.1 3.2 3.3 3.4 3.5 PORT PINS ........................................................................................................................................9 NON PORT PINS ............................................................................................................................ 11 PIN INPUT/OUTPUT CIRCUIT ...................................................................................................... 13 SELECTION OF MASK OPTIONS ................................................................................................. 16 PROCESSING OF UNUSED PINS ................................................................................................ 17
4. 5. 6.
MEMORY CONFIGURATION ................................................................................................. 18 EEPROM ....................................................................................................................................21 PERIPHERAL HARDWARE FUNCTIONS ............................................................................... 22
6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 PORT ............................................................................................................................................... 22 CLOCK GENERATOR CIRCUIT ..................................................................................................... 23 CLOCK OUTPUT CIRCUIT ............................................................................................................. 24 BASIC INTERVAL TIMER .............................................................................................................. 25 WATCH TIMER ............................................................................................................................... 26 TIMER/EVENT COUNTER ............................................................................................................. 27 SERIAL INTERFACE ....................................................................................................................... 29 A/D CONVERTER .......................................................................................................................... 31 MULTI-FUNCTION TIMER (MFT) ................................................................................................. 32
6.10 BIT SEQUENTIAL BUFFER ........................................................................................................... 34
7. 8. 9.
INTERRUPT FUNCTIONS ....................................................................................................... 34 STANDBY FUNCTIONS .......................................................................................................... 36 RESET FUNCTION .................................................................................................................. 37
10. INSTRUCTION SET ................................................................................................................. 39 11. ELECTRICAL SPECIFICATIONS ............................................................................................. 45 12. PERFORMANCE CURVE ......................................................................................................... 59 13. PACKAGE DRAWINGS ........................................................................................................... 61 14. RECOMMENDED SOLDERING CONDITIONS ...................................................................... 63 APPENDIX A. COMPARISON BETWEEN PD75048 AND 75028/75008 FUNCTIONS .......... 64 APPENDIX B. DEVELOPMENT TOOLS ....................................................................................... 65
4
PD75048
1. PIN CONFIGURATION (TOP VIEW)
* 64-PIN PLASTIC SHRINK DIP (750 mil)
SB1/SI/P03 SB0/SO/P02 SCK/P01 INT4/P00 BUZ/P23 PCL/P22 PCO/P21 PTO0/P20 MAT/P103 MAZ/P102 MAI/P101 MAR/P100 RESET X1 X2 IC XT1 XT2 VDD AVDD AVREF+ AVREF- AN7 AN6 AN5 AN4 AN3/P113 AN2/P112 AN1/P111 AN0/P110 AVSS TI0/P13
1 2 3 4 5 6 7 8 9 10 11 12 13
64 63 62 61 60 59 58 57 56 55 54 53 52
VSS P30 P31 P32 P33 P40 P41 P42 P43 P50 P51 P52 P53 P60/KR0 P61/KR1 P62/KR2 P63/KR3 P70/KR4 P71/KR5 P72/KR6 P73/KR7 P80 P81 P82 P83 P90 P91 P92 P93 P10/INT0 P11/INT1 P12/INT2
PD75048CW-*
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
IC : Internally Connected (Connect directly to VDD)
XXX
**
5
PD75048
* 64-PIN PLASTIC QFP ( 14 mm)
P60/KR0
P61/KR1
P62/KR2
P63/KR3
P70/KR4
P71/KR5
P72/KR6
P73/KR7
P50
P51
P52
P53
P80
P81
P82
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P43 P42 P41 P40 P33 P32 P31 P30 VSS SB1/SI/P03 SB0/SO/P02 SCK/P01 INT4/P00 BUZ/P23 PCL/P22 PPO/P21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P90 P91 P92 P93 P10/INT0 P11/INT1 P12/INT2 TI0/P13 AVSS AN0/P110 AN1/P111 AN2/P112 AN3/P113 AN4 AN5 AN6
RESET
AVREF+
AVREF-
AVDD
XT1
XT2
VDD
X1
X2
IC
MAT/P103
MAZ/P102
MAI/P101
IC : Internally Connected (Connect directly to VDD)
6
MAR/P100
PTO0/P20
AN7
P83
PD75048GC-*XXX AB8 * *-AB8
PD75048
PIN IDENTIFICATION
P00-03 P10-13 P20-23 P30-33 P40-43 P50-53 P60-63 P70-73 P80-83 P90-93 P100-103 P110-113 KR0-7 SCK SI SO SB0, 1 RESET TI0 PTO0 BUZ PCL INT0,1,4 INT2 X1, 2 XT1, 2 MAR MAI MAZ MAT PPO AN0-7 AVREF+ AVREFAVDD AVSS VDD VSS : Port0 : Port1 : Port2 : Port3 : Port4 : Port5 : Port6 : Port7 : Port8 : Port9 : Port10 : Port11 : Key Return : Serial Clock : Serial Input : Serial Output : Serial Bus 0, 1 : Reset Input : Timer Input 0 : Programmable Timer Output 0 : Buzzer Clock : Programmable Clock : External Vectored Interrupt 0, 1, 4 : External Test Input 2 : Main System Clock Oscillation 1, 2 : Subsystem Clock Oscillation 1, 2 : Reference Integration Control : Integration Control : Autozero Control : External Comparate Timing Input : Programmable Pulse Output ... : MFT timer mode : Analog Input 0-7 : Analog Reference (+) : Analog Reference (-) : Analog VDD : Analog VSS : Positive Power Supply : Ground : Analog input : Analog reference voltage (+) input (AVDD) : Analog reference voltage (-) input (AVSS) : A/D converter positive power supply : A/D converter GND : Positive power supply : GND MFT A/D mode : Port 0 : Port 1 : Port 2 : Port 3 : Port 4 : Port 5 : Port 6 : Port 7 : Port 8 : Port 9 : Port 10 : Port 11 : Key interrupt input : Serial clock input/output : Serial data input : Serial data output : Serial bus input/output : Reset input : External event pulse input : Timer/event counter output : Arbitrary frequency output : Clock output : External vector interrupt input : External test input : Main system clock oscillation pin : Subsystem clock oscillation pin : Reference integration signal output : Integration signal output : Autozero signal output : External comparator signal input : Pulse output ... MFT timer mode MFT A/D mode
Remarks : MFT: Multi-function timer
7
BASIC INTERVAL TIMER INTBT TI0/P13 PTO0/P20 TIMER /COUNTER #0 INTT0 SI/SB1/P03 SO/SB0/P02 SCK/P01 INTCSI INT0/P10 INT1/P11 INT2/P12 INT4/P00 KR0-KR3/P60-P63 KR4-KR7/P70-P73 BUZ/P23 8 WATCH TIMER INTW AVDD AVREF+ AVREF- AVSS AN0-AN3/P110-P113 AN4-AN7 MAR/P100 MAI/P101 MAZ/P102 MAT/P103 PPO/P21 INTMFT VDD VSS RESET MULTI- FUNCTION TIMER 8 EEPROM 1024 x 4 BITS A/D CONVERTER fx/2N CLOCK OUTPUT CONTROL CLOCK GENERATOR SUB MAIN DATA MEMORY SERIAL INTERFACE BANK
BIT SEQ. BUFFER
8
2. BLOCK DIAGRAM
PORT 0 PROGRAM COUNTER ALU SP CY PORT 1
4
P00-P03
4
P10-P13
PORT 2
4
P20-P23
PORT 3
4
P30-P33
GENERAL REG. INTERRUPT CONTROL ROM PROGRAM MEMORY 8064x8 BITS DECODE AND CONTROL
PORT 4
4
P40-P43
PORT 5 RAM 512 x 4 BITS PORT 6
4
P50-P53
4
P60-P63
PORT 7
4
P70-P73
PORT 8
4
P80-P83
PORT 9 CPU CLOCK STAND BY CONTROL PORT 10
4
P90-P93
CLOCK DIVIDER
4
P100-P103
PORT 11 PCL/P22 XT1 XT2 X1 X2
4
PD75048
P110-P113
PD75048
3. PIN FUNCTIONS
3.1 PORT PINS
Input/ Output Circuit TYPE*1 B
Also Served Pin Name Input/Output As Input/ Output Input/ Output Input/ Output Input/ Output
Function
8-Bit I/O
When Reset
P00
INT4
P01 P02
SCK SO/SB0
4-bit input/output port(PORT0) Pull up resistros can be specified in 3-bit units for the P01 to P03 pins by software.
F -A X Input F -B
P03 P10 P11
SO/SB1 INT0 INT1 With noise elimination function 4-bit input port(PORT1) Internal pull-up resistors can be specified in 4-bit units by software. X Input
M -C
Input P12 P13 P20 P21 P22 P23 P30* P31*
2
B -C
INT2 TI0 PTO0 Input/ Output PPO PCL BUZ -- Input/ Output -- -- --
4-bit input/output port(PORT2) Internal pull-up resistors can be specified in 4-bit units by software.
X
Input
E -B
2
P32*2 P33*2
Programmable 4-bit input/output port (PORT3) This port can be specified for input/ output in bit units. Internal pull-up resistors can be specified in 4-bit units by software. N-ch open-drain 4-bit input/output port (PORT4) Internal pull-up resistors can be specified in 4-bit units (by mask option). Resistive voltage is 10V in the opendrain mode. N-ch open-drain 4-bit input/output port (PORT5) Internal pull-up resistors can be specified in bit units (by mask option). Resistive voltage is 10V in the opendrain mode.
X
Input
E -B
P40-43*2
Input/ Output
--
High level (with internal pull-up register) or high impedance High level (with internal pull-up register) or high impedance
M
P50-53*2
Input/ Output
--
M
*1: Circles indicate Schmitt trigger inputs. 2: Can directly drive LED.
9
PD75048
(cont'd)
Input/ Output Circuit TYPE*1
Pin Name Input/Output Also Served As P60 P61 P62 P63 P70 P71 P72 P73 Input/ Output Input/ Output KR0 KR1 KR2 KR3 KR4 KR5 KR6 KR7
Function
8-Bit I/O
When Reset
Programmable 4-bit input/output port (PORT6) This port can be specified for input/ output in bit units. Internal pull-up resistors can be specified in 4-bit units by software.
Input
F -A
4-bit input/output port(PORT7) Internal pull-up resistors can be specified in 4-bit units by software.
Input
F -A
P80-83
Input/ Output
--
4-bit input/output port(PORT8) Internal pull-up resistors can be specified in 4-bit units by software. X
Input
E-B
P90-93
Input/ Output
--
4-bit input/output port(PORT9) Internal pull-down resistors can be specified in 4-bit units by software. N-ch open-drain 4-bit input/output port (PORT10) Internal pull-up resistors can be specified in bit units (by mask option). Resistive voltage is 10V in the opendrain mode. X
Input
E-D
P100 P101 P102 P103 P110 P111 P112 P113 Input Input/ Output
MAR MAI MAZ MAT AN0 AN1
High level (with internal pull-up resistor) or high impedance
M
4-bit input port(PORT11) AN2 AN3
Input
Y-A
*1: Circles indicate Schmitt trigger inputs.
10
PD75048
3.2 NON PORT PINS
Input/ Output Circuit TYPE*1 B-C E-B E-B E-B F-A F-B M-C B
Also Served Pin Name Input/Output As TI0 PTO0 PCL BUZ SCK SO/SB0 SI/SB1 INT4 INT0 Input INT1 P11 Input Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input P13 P20 P22 P23 P01 P02 P03 P00 P10
Functon
When Reset
Timer/event counter external event pulse input Timer/event counter output Clock output Arbitrary frequency output(for buzzer or for trimming the system clock) Serial clock input/output Serial data output Serial bus input/output Serial data input Serial bus input/output Edge detection vector interrupt input (both rising and falling edge detection are effective) Edge detection vector interrupt input (detection edge is selectable) Clock synchronous
Input Input Input Input Input Input Input Input
Input Asynchronous
B-C
INT2
Input
P12
Edge detection vector interrupt input (rising edge is detected.)
Asynchronous
Input
B-C
KR0-KR3 KR4-KR7 MAR MAI MAZ MAT PPO
Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output
P60-63 P70-73 P100 P101 P102 P103 P21
Parallel falling edge detection testable input Parallel falling edge detection testable input Reference integration signal output In the MFT integration type A/ D converter mode Integration signal output
Input Input
F-A F-A
*2 Auto zero signal output Comparator input
M
In the MFT timer mode
Timer pulse output
Input
E-B
*1: Circles indicate Schmitt trigger inputs. 2:
High level (with internal pull-up resistor) or high impedence MFT: Multi-function timer
Remarks:
11
PD75048
(cont'd)
Input/ Output Circuit TYPE*1 Y-A 8-bit analog input -- Input Input -- -- -- -- -- -- Pins only for A/D converter Reference voltage input (AVDD side) Reference voltage input (AVSS side) Positive power supply GND A crystal/ceramic resonator for the main system clock is connected across these pins. When using the external clock, the X1 pin inputs the external clock, and the X2 pin inputs the reverse phase of the external clock signal. A crystal resonator for the subsystem clock is connected across these pins. When using the external clock, the XT1 pin inputs the external clock, and the XT2 pin inputs the reverse phase of the external clock signal. The XT1 pin can be used as a 1-bit input(test) pin. System reset input Internally Connected. Should be connected directly to VDD. Positive power supply GND -- -- -- -- Input Y Z-A Z-A -- --
Pin Name Input/Output Also Served As AN0-AN3 Input AN4-AN7 AVREF+ AVREFAVDD AVSS --
Function
When Reset
X1, X2
Input
--
--
--
XT1, XT2
Input
--
--
--
RESET IC VDD VSS
Input -- -- --
-- -- -- --
-- -- -- --
B -- -- --
*1: Circles indicate Schmitt trigger inputs.
12
PD75048
3.3 PIN INPUT/OUTPUT CIRCUITS
The following shows a simplified input/output circuit diagram for each pin of the PD75048.
TYPE A (for TYPE E-B) TYPE D (for TYPE E-B, F-A)
VDD data
P-ch
VDD P-ch OUT
IN
N-ch
output disable
N-ch
Input buffer of CMOS standard
Push-pull output that can be set in the output high-impedance state (both P-ch and N-ch are off)
TYPE B
TYPE E-B
VDD P.U.R. P.U.R. enable IN data Type D output disable IN/OUT P-ch
Type A
Schmitt trigger input with hysteresis characteristics
P.U.R. : Pull-Up Resistor
13
PD75048
TYPE B-C
TYPE E-D
data VDD P.U.R. P-ch P.U.R. enable output disable Type D
IN/OUT
Type A
IN
P.U.R. enable
N-ch P.D.R.
P.U.R. : Pull-Up Resistor
P.D.R. : Pull-Down Resistor
TYPE F-A
TYPE M-C
VDD P.U.R. P.U.R. enable data Type D output disable P-ch P.U.R. enable
VDD P.U.R. P-ch IN/OUT IN/OUT data output disable N-ch
Type B
P.U.R. : Pull-Up Resistor
P.U.R. : Pull-Up Resistor
14
PD75048
TYPE F-B
VDD P.U.R. P.U.R. enable VDD P-ch data output disable IN/OUT N-ch output disable (N) P-ch
TYPE Y
output disable (P)
AVDD IN AVDD Sampling C AVSS P-ch N-ch + -
AVSS Reference voltage (from a voltage tap of series resistor string) input enable
P.U.R. : Pull-Up Resistor
TYPE M
TYPE Y-A
VDD P.U.R. enable (Mask Option) data output disable IN instruction IN/OUT Input buffer N-ch (resistive voltage: +10 V) AVDD IN AVDD Sampling C P-ch N-ch + -
Middle voltage input buffer (resistive voltage: +10 V) P.U.R. : Pull-Up Resistor
AVSS
AVSS Reference voltage (from a voltage tap of series resistor string)
15
PD75048
TYPE Z-A
AVREF+
Reference voltage
AVREF-
3.4
SELECTION OF MASK OPTIONS
The following mask options are available:
Pin P40 - P43, P50 - P53, P100 - P103 XT1, XT2 1 w/pull-up resistor (can be specified bitwise) w/feedback resistor (with subsystem clock used) Mask Option 2 w/o pull-up resistor (can be specified bitwise) w/o feedback resistor (without subsystem clock used)
1
2
16
PD75048
3.5 PROCESSING OF UNUSED PINS
Pin P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0-P12/INT2 P13/TI0 P20/PTO0 P21/PPO P22/PCL P23/BUZ P30-P33 P40-P43 P50-P53 P60/KR0-P63/KR3 P70/KR4-P73/KR7 P80-P83 P90-P93 P100/MAR P101/MAI P102/MAZ P103/MAT P110/AN0-P113/AN3 AN4-AN7 AVREF+ AVREFAVSS AVDD XT1 XT2 IC Connect to VDD Connect to VSS or VDD Open Connect directly to VDD Connect to VSS Connect to VSS or VDD Input: Connect to VSS or VDD Output: Open Connect to VSS Connect to VSS or VDD Connect to Vss Recommended Condition
5
17
PD75048
4. MEMORY CONFIGURATION * Program memory (ROM)...8064 x 8 bits (0000H-1F7FH)
* 0000H, 0001H: reset * 0002H-000FH: Vector table to which address from which program is started is written after interrupt * 0020H-007FH: Table area referenced by GETI instruction Vector table to which address from which program is started is written after
* Data memory
* Data area Static RAM....512 x 4 bits (000H-1FFH) EEPROM....1024 x 4 bits (400H-7FFH) * Peripheral hardware area....128 x 4 bits (F80H-FFFH)
18
PD75048
Address 7 0000H MBE 6 0 5 0 Internal reset start address (upper 5 bits) Internal reset start address (lower 8 bits) 0002H MBE 0 0 INTBT/INT4 start address (upper 5 bits) INTBT/INT4 start address (lower 8 bits) 0004H MBE 0 0 INT0 start address (upper 5 bits) INT0 start address (lower 8 bits) 0006H MBE 0 0 INT1 start address (upper 5 bits) INT1 start address (lower 8 bits) 0008H MBE 0 0 INTCSI start address (upper 5 bits) INTCSI start address (lower 8 bits) 000AH MBE 0 0 INTT0 start address (upper 5 bits) INTT0 start address (lower 8 bits) 000CH MBE 0 0 INTMFT start address (upper 5 bits) INTMFT start address (lower 8 bits) 000EH MBE 0 0 INTEE/INTOW start address (upper 5 bits) INTEE/INTOW start address (lower 8 bits) BRCB ! caddr instruction branch address CALL ! addr instruction subroutine entry address CALLF ! faddr instruction entry address 0
BR ! addr instruction branch address
0020H GETI instruction reference table 007FH 0080H
BR $addr instruction relational branch address (-15 to -1, +2 to +16)
07FFH 0800H Branch destination address and subroutine entry address for GETI instruction 0FFFH 1000H BRCB ! caddr instruction branch address 1F7FH
Fig. 4-1 Program Memory Map
19
PD75048
Data memory 000H General-purpose register area Stack area Data area Static RAM (512 x 4) 0FFH 100H 256 x 4 1FFH 007H 256 x 4 (248 x 4) (8 x 4)
Memory bank
0
1
Unmapped
400H 256 x 4 4FFH 500H 256 x 4 Data area EEPROM (1024 x 4) 5FFH 600H 256 x 4 6FFH 700H 256 x 4 7FFH 7 6 5 4
Unmapped
F80H Peripheral hardware area FFFH 128 x 4 15
Fig. 4-2 Data Memory Map
20
PD75048
5. EEPROM
The PD75048 contains the 1024-word x 4-bit EEPROM (Electrically Erasable PROM). The EEPROM of the PD75048 has the following characteristics. * * * The EEPROM can retain its contents even if the power is turned off. In the same manner as the static RAM, data can be manipulated (auto-erase/write/read) in 4-bit or 8-bit units by using a memory manipulation instruction The contens of EEPROM are automatically erased or written by hardware, so that the overhead of the software is alleviated.
* *
Write time .... 10 ms. Number of write operation100,000 times (guaranteed). When write operation is completed an interrupt occurs. When overwrite is executed. (Write operation is executed during write operation)
*
Write operation can be controlled by interrupt.
* *
*
Whether or not the EEPROM is possible to be written can be checked by individually checking the write status flag.
21
PD75048
6. PERIPHERAL HARDWARE FUNCTIONS
6.1 PORT
I/O ports are classified into the following three inds: * CMOS input (PORT0, 1, 11) * CMOS I/O (PORT2, 3, 6, 7, 8, 9) Total : : 12 24 12 48
* N-ch open-drain I/O (PORT4, 5, 10) :
Table 6-1 Port Function
Port (Symbol) PORT0 PORT1 PORT3* PORT6 4-bit input/output PORT2 PORT7 Function 4-bit input Operation/Feature Can be read or tested regardless of the operation mode of the shared pin. Can be specified for input/output in 1-bit units. Can be specified for input/output in 4-bit units. Ports 6 and 7 can be paired to input/ output data in 8-bit units. Remarks Also serves as the SO/SB0, SI/SB1, SCK, INT0 to 2, INT4, and TI0 pins Port 6 can also serve as the KR0 to KR3 pins. Port 2 can also serve as the PTO0, PPO, PCL, and BUZ pins. Also serves as the KR4 to KR7 pins.
Whether or not the internal pull-up resistor is provided can be specified for each bit by mask option.
PORT4* PORT5* PORT10* PORT8 PORT9 PORT11
Can be specified for input/output 4-bit input/output in 4-bit units. Ports 4 and 5 can (N-ch open-drain, be paired to input/output data in can sustain with 10V) 8-bit units. 4-bit input/output 4-bit input Can be specified for input/output in 4-bit units. 4-bit input-only port.
Port 10 can also serve as the MAR, MAI, MAZ, and MAT pins.
Port 11 can also serve as the AN0 to AN3 pins.
*: Can directly drive LED.
22
PD75048
6.2 CLOCK GENERATOR CIRCUIT
The operation of the clock generator circuit is determined by the processor clock control regiser (PPC) and system clock control register (SCC). This circuit can generate two types of clocks: main system clock and subsystem clock. In addition, it can also change the instruction execution time. * 0.95 s, 1.91 s, 15.3 s (main system clock: 4.19 MHz) * 122s (subsystem clock: 32.768 kHz)
XT1 VDD XT2 Subsystem clock oscillator fXT Watch timer . . . . . . Multi-function timer Basic interval timer (BT) Timer/event counter Serial interface Watch timer A/D converter (successive approximation) . INT0 noise rejecter circuit . Clock output circuit
X1 VDD Main system clock oscillator fX 1/2 to 1/4096 Frequency divider 1/2 1/16
X2
WM.3 SCC SCC3
Selector
Oscillator disable signal
Selector
Frequency divider 1/4 . CPU . INT0 noise rejecter circuit . Clock output circuit
SCC0
Internal bus
PCC PCC0 PCC1 4 PCC2 HALT* PCC3 STOP* R Q HALT F/F S
PCC2, PCC3 clear signal
STOP F/F Q S
Wait release signal from BT RESET signal
R
Standby release signal from interrupt control circuit
Remarks1: 2: 3: 4: 5: 6: 7:
fX = Main system clock frequency fXT = Subsystem clock frequency = CPU clock PCC: Processor clock control register SCC: System clock control register * indicates instruction execution. One clock cysle (tCY) of is one machine cycle of an instruction. For tCY, refer to AC characteristics in 11. ELECTRICAL SPECIFICATIONS.
Fig. 6-1 Clock Generator Block Diagram
23
PD75048
6.3 CLOCK OUTPUT CIRCUIT
The clock output circuit outputs clock pulse from the P22/PCL pin. This clock pulse is used for supplying clock pulses to the remote control output, peripheral LSIs, etc. * Clock output (PCL): , 524 kHz, 65.5 kHz (at 4.19 MHz)
From the clock generator F fX/23 Selector fX/24 fX/26 PCL/P22 Output buffer
PORT2.2 CLOM3 CLOM2 CLOM1 CLOM0 CLOM
P22 output latch
Bit 2 of PMGB
Port 2 input/ output mode specification bit
4 Internal bus
Fig. 6-2 Clock Output Circuit Configuration
Remarks:
A measures to prevent outputting narrow width pulse when selecting clock output enable/disable is taken.
24
PD75048
6.4 BASIC INTERVAL TIMER
The basic interval timer has these functions: * Interval timer operation which generates a reference time interrupt * Watchdog timer application which detects a program runaway * Selects the wait time for releasing the standby mode and counts the wait time * Reads out the count value
From the clock generator Clear fX/25 Clear
fX/27 MPX fX/29 BT Basic interval timer (8-bit frequency divider circuit)
Set signal
BT interrupt request flag
fX/212
Vector interrupt request IRQBT signal
3
Wait release signal for standby release BTM0 BTM
BTM3
BTM2
BTM1
*SET1
4 Internal bus
8
Remarks : *: Instruction execution
Fig. 6-3 Basic Interval Timer Configuration
25
PD75048
6.5 WATCH TIMER
The PD75048 has a built-in 1-ch watch timer. The clock timer has the following functions. * Sets the test flag (IRQW) with 0.5sec interval. The standby mode can be released by IRQW. * 0.5 second interval can be generated either from the main system clock or subsystem clock. * Time interval can be advanced to 128 times faster (3.91 ms) by setting the fast mode. This is convenient for program debugging, test, etc. * Arbitrary frequency (2.048kHz/4.096kHz/32.768kHz) can be output to the P23/BUZ pin. This can be used for beep and system clock frequency trimming. * The frequency divider circuit can be cleared so that zero second clock start is possible.
fW (256 Hz:3.91 ms) 27 fX 128 (32.768 kHz) Selector fXT (32.768 kHz) INTW IRQW set signal
From the clock generator
fW (32.768 kHz)
Frequency divider 4 kHz 2 kHz Clear
fw 214
Selector
(
)
(
2 Hz 0.5 sec
)
Selector
Output buffer P23/BUZ
WM WM7 0 WM5 WM4 WM3 WM2 WM1 WM0
PORT2.3
P23 output latch
Bit 2 of PMGB
Port 2 input/output mode
8
Bit test instruction
Internal bus
( ) is for fX = 4.194304 MHz, fXT = 32.768 KHz.
Fig. 6-4 Clock Timer Block Diagram
26
PD75048
6.6 TIMER/EVENT COUNTER
The PD75048 has a built-in 1-ch timer/event counter. The timer/event counter has the following functions. * Programmable interval timer operation * Outputs square-wave signal of an arbitrary frequency to the PTO0 pin. * Event counter operation * Divides the TI0 pin input in N and outputs to the PTO0 pin (frequency divider operation). * Supplies serial shift clock to the serial interface circuit. * Count condition read out function
27
28
Internal bus 8 SET1* TM0 8 8 TMOD0 TOE0 TO enable flag Coincidence PORT2.0 P20 output latch Bit 2 of PGMB
Port 2 input/ output mode
TM07 TM06 TM05 TM04 TM03 TM02 TM01 TM00
Modulo register (8)
PORT1.3
8 Comparator (8)
To serial interface
TOUT F/F Reset Output buffer
P20/PTO0
Input buffer P13/TI0 From the clock generator MPX
8 T0 Count register (8) CP Clear Timer operation start signal
(
INTT0 IRQT0 set signal
)
RESET IRQT0 clear signal *:Instruction execution
Fig. 6-5 Timer/Event Counter Block Diagram
PD75048
PD75048
6.7 SERIAL INTERFACE
The PD75048 is equipped with an 8-bit clocked serial interface that operates in the following four modes: * Operation stop mode * Three-line serial I/O mode * Two-line serial I/O mode * SBI mode (serial bus interface mode)
29
Selector
P02/SO/SB0
Selector
Busy/ acknowledge output circuit
Bus release/ command/ acknowledge detector circuit P01/SCK
RELD CMDD ACKD
ACKT ACKE BSYE
30
Internal bus 8/4 CSIM Bit test 8 8 8
Slave address register (SVA)
Bit manipulation (8) RELT CMDT
SET CLR
Bit test SBIC
Address comparator P03/SI/SB1 Shift register (SIO)
Coincidence signal (8)
SO latch
(8)
D
Q
Serial clock counter P01 output latch
INTCSI control circuit
(
Serial clock selector
INTCSI IRQCSI set signal
)
Serial clock control circuit
fX/23 fX/24 fX/26 TOUT F/F (from timer/ event counter) External SCK
PD75048
Fig. 6-6 Serial Interface Block Diagram
PD75048
6.8 A/D CONVERTER
The PD75048 has an 8-bit precision successive approximation A/D converter with 8 analog input channels (AN0 to AN7).
Internal bus
0
ADM6 ADM5 ADM4
SOC
EOC
0
0
ADM
8
AN0/P110 AN1/P111 Sample hold circuit AN2/P112
Multiplexer
Control circuit
AN3/P113 AN4 AN5 AN6 AN7
+ - Comparator
SA register (8)
8
Tap decoder
AVREF+ R/2 R R R R/2 Serial resister string AVREF-
Fig. 6-7 A/D Converter Block Diagram
31
PD75048
6.9 MULTI-FUNCTION TIMER (MFT)
The PD75048 contains 1 channel of multi-function timer (MFT). The MFT has the following four modes and functions: * 8-bit timer mode
* *
Functions as programmable interval timer Outputs square waves of arbitrary frequency to the PPO pin
* PWM mode
*
Outputs 6/7/8-bit precision PWM signal to the PPO pin
* 16-bit free running timer mode
* *
Functions as interval timer which generates an interrupt with specified interval Can be used as one-shot timer
* Integration type A/D converter mode
* *
Outputs 16-bit integration type A/D converter control signal 13/14/15/16-bit precision selectable
32
Internal bus
Clear MAT/P103 Edge selector
8
8
Output latch
P21 P100P101 P102
Input/ output mode register
Selector
Count register (MFTL) Modulo latch
Integration type A/D converter controller
Coinci -dence
MAZ/P102 MAI/P101 MAR/P100 PPO/P21
fX/2 fX/23 fX/25 fX/27 fX/29 fX/211 Selector Count register (MFTH) Tap selector MPX Comparator
MFT F/F Overflow Interrupt selector
8
(
INTMFT IRQMFT set signal
)
RESET Selector IRQMFT clear signal
MFTM7 MFTM6 MFTM5 MFTM4 MFTM3 MFTM2 MFTM1 MFTM0 8
MFTM
MFTC3 MFTC2 MFTC1 MFTC0 1/4
MFTC
PD75048
Internal bus
Fig. 6-8 Multi-Function Timer Block Diagram
33
PD75048
6.10 BIT SEQUENTIAL BUFFER .... 16 BITS
The bit sequential buffer is a data memory specifically provided for bit manipulation. With this buffer, addresses and bit specifications can be sequentially up-dated in bit manipulation operation. Therefore, this buffer is very useful for processing long data in bit units.
Address Bit Symbol 3
FC3H 2 BSB3 1 0 3
FC2H 2 BSB2 1 0 3
FC1H 2 BSB1 1 0 3
FC0H 2 BSB0 1 0
L register
L=F
L=C L=B INCS L
L=8 L=7 DECS L
L=4 L=3
L=0
Remarks:
For the pmem.@L addressing, the specification bit is shifted according to the L register.
Fig. 6-9 Bit Sequential Buffer Format 7. INTERRUPT FUNCTIONS
The PD75048 has 9 different interrupt sources. In addition to that, multiple interrupt by software control is also possible. The PD75048 is also provided with two types of test sources, of which INT2 was two types of edge detection testable inputs. The interrupt control circuit of the PD75048 has these functions: * Hardware controlled vector interrupt function which can control whether or not to accept an interrupt by using the interrupt flag (IExxx) and interrupt master enable flag (IME). * The interrupt start address can be arbitrarily set. * Interrupt request flag (IRQxxx) test function (an interrupt generation can be confirmed by means of software). * Standby mode release (Interrupts to be released can be selected by the interrupt enable flag).
34
Internal bus 2 IM2 1 IM1 3 IM0 Interrupt enable flag (IExxx) IME IST0
INT4 /P00 INT0 /P10 INT1 /P11
*
INT BT Both edge detection circuit Edge detection circuit Edge detection circuit INTCSI INTT0 INTMFT INTEE INTOW INTW
Decoder IRQBT IRQ4 IRQ0 IRQ1 IRQCSI IRQT0 IRQMFT IRQEE IRQOW IRQW Priority control circuit VRQn
Vector table address generator
INT2 / P12
Selector
Rising edge detection circuit Falling edge detection circuit
IRQ2
Standby release signal
KR0/P60 KR7/P73
PD75048
IM2
* : Noise elimination circuit
Fig. 7-1 Interrupt Control Circuit Block Diagram
35
PD75048
8. STANDBY FUNCTIONS
The PD75048 has two different standby modes (STOP mode and HALT mode) to reduce the power consumption while waiting for program execution.
Table 8-1 Each Status in Standby Mode
STOP Mode Setting Instruction System Clock for Setting Operation Status Clock Generator Basic Interval Timer Serial Interface STOP instrtuction Can be set only when operating on the main system clock Only the main system clock stops its operation No operation HALT Mode HALT Instruction Can be set either with the main system clock or the subsystem clock Only the CPU clock stops its operation (oscillation continues) Operates only when main system clock oscillates (Sets IRQBT at reference time interval) Operates only when external SCK input is selected as serial clock, or when main system clock oscillates Operates only when TI0 pin input is selected as count clock, or when main system clock oscillates Can operate Can operate * Can operate * Can operate *
Can operate only when the external SCK input is selected for the serial clock Can operate only when the TI0 pin input is selected for the count clock Can operate when fXT is selected as the count clock No operation No operation No operation INT1, INT2, and INT4 can operate. Only INT0 can not operate. No operation An interrupt request signal from a hardware whose operation is enabled by the interrupt enable flag or the RESET input.
Timer/Event Counter Watch Timer A/D Convertor Multi Function Timer EEPROM External Interrupt CPU Release Signal
An interrupt request signal from a hardware whose operation is enabled by the interrupt enable flag or the RESET input.
*: Operation is possible only when the main system clock is operating.
36
PD75048
9. RESET FUNCTION
When the RESET signal is input, the PD75048 is reset and each hardware is initialized as indicated in Table 9-1. Fig. 9-1 shows the reset operation timing.
Wait (31.3ms/4.19MHz) RESET input
Operation mode or standby mode
HALT mode
Operation mode
Internal reset operation
Fig. 9-1 Reset Operation by RESET Input
Table 9-1 Status of Each Hardware after Reset (1/2)
Hardware Program Counter (PC) RESET Input in Standby Mode The contents of the lower 5 bits of address 0000H of the program memory are set to PC12-8, and the contents of address 0001H are set to PC7-0. Retained 0 0 The contents of bit 7 of address 0000H of the program memory is set to MBE. Undefined Retained * Contents of address being written is undefined. 0 Retained 0 Undefined 0 0 FFH 0 0, 0 0 RESET Input During Operation The contents of the lower 5 bits of address 0000H of the program memory are set to PC12-8, and the contents of address 0001H are set to PC7-0. Undefined 0 0 The contents of bit 7 of address 0000H of the program memory is set to MBE. Undefined Undefined Contents of address being written is undefined. 0 Undefined 0 Undefined 0 0 FFH 0 0, 0 0
PSW
Carry Flag (CY) Skip Flag (SK0-2) Interrupt Status Flag (IST0) Bank Enable Flag (MBE)
Stack Pointer (SP) Data Memory (RAM) Data Memory EEPROM (EEPROM) EEPROM Write Control Register General-Purpose Register (X, A, H, L, D, E, B, C) Bank Selection Register (MBS) Basic Interval Counter (BT) Timer Mode Register (BTM) Timer/Event Counter Counter (T0) Modulo Register (TMOD0) Mode Register (TM0) TOE0, TOUT F/F Watch Timer Mode Register (WM)
*: The data at the addresses 0F8H-0FDH of data memory is undefined by RESET input.
37
PD75048
Table 9-1 Status of Each Hardware after Reset (2/2)
Hardware Serial Interface Shift Register (SIO) Operation Mode Register (CSIM) SBI Control Register (SBIC) Slave Address Register (SVA) Clock Generator, Clock Output Circuit Processor Clock Control Register (PCC) System Clock Control Register (SCC) Clock Output Mode Register (CLOM) RESET Input in Standby Mode Retained 0 0 Retained 0 0 0 Undefined 0 0 0 0, 0, 0 Off Clear (0) 0 RESET Input During Operation Undefined 0 0 Undefined 0 0 0 Undefined 0 0 0 0, 0, 0 Off Clear (0) 0
5
Interrupt request flag (IRQxxx) Interrupt Function
IRQ1, IRQ2, IRQ4 Other than above
Interrupt Enable Flag (IExxx) Interrupt Master Enable Flag (IME) INT0, INT1, INT2 Mode Registers (IM0, IM1, IM2)
Digital Port
Output Buffer Output Latch Input/Output Mode Register (PMGA, PMGB, PMGC) Pull-up Resistor Specification Register (POGA, POGB) Pull-down Resistor Specification Register (PDGB)
0
0
0
0
Multi-Function Counter (MFTL) Timer Counter (MFTH) Mode Register (MFTM) Control Register (MFTC) A/D Converter Mode Register (ADM) SA Register (SA) Bit sequential buffer (BSB0-3)
FFH 0 0 0 04H Retained Retained
FFH 0 0 0 04H Undefined Undefined
38
PD75048
10. INSTRUCTION SET
(1) Operand representation and description Describe one or more operands in the operand field of each instruction according to the operand representation and description methods of the instruction (for details, refer to RA75X Assembler Package User's Manual - Language (EEU-730). With some instructions, only one operand should be selected from several operands. The uppercase characters, +, and - are keywords and must be described as is. Describe an appropriate numeric value or label as immediate data. The symbols of the register flags can be described in the places of mem, fmem, pmem, and bit. (For details, refer to PD75048 User's Manual (IEU-704). However, fmem and pmem restricts the label that can be described.
Representation reg reg1 rp rp1 rp2 rpa rpa1 n4 n8 mem* bit fmem pmem addr caddr faddr taddr PORTn IExxx MBn Description X, A, B, C, D, E, H, L X, B, C, D, E, H, L XA, BC, DE, HL BC, DE, HL BC, DE HL, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or label 2-bit immediate data or label
FB0H to FBFH, FF0H to FFFH immediate data or label FC0H to FFFH immediate data or label
0000H to 1F7FH immediate data or label 12-bit immediate data or label 11-bit immediate data or label 20H to 7FH immediate data (where bit0=0) or label PORT0 to PORT11 IEBT, IECSI, IET0, IE0, IE1, IE2, IE4, IEW, IEMFT, IEEE, IEOW MB0, MB1, MB4, MB5, MB6, MB7, MB15
*: Only even addresses can be described as mem for 8-bit data processing.
39
PD75048
(2) Legend of operation field A B C D E H L X XA BC DE HL PC SP CY PSW MBE IME IExxx MBS PCC . (xx) xxH : A register; 4-bit accumulator : B register; 4-bit accumulator : C register; 4-bit accumulator : D register; 4-bit accumulator : E register; 4-bit accumulator : H register; 4-bit accumulator : L register; 4-bit accumulator : X register; 4-bit accumulator : Register pair (XA); 8-bit accumulator : Register pair (BC); 8-bit accumulator : Register pair (DE); 8-bit accumulator : Register pair (HL); 8-bit accumulator : Program counter : Stack pointer : Carry flag; or bit accumulator : Program status word : Memory bank enable flag : Interrupt master enable flag : Interrupt enable flag : Memory bank selector register : Processor clock control register : Delimiter of address and bit : Contents addressed by xx : Hexadecimal data
PORTn : Port n (n = 0 to 11)
40
PD75048
(3) Symbols in addressing area field
*1 *2 *3 MB = MBE . MBS (MBS = 0, 1, 15) MB = 0 MBE = 0 : MB = 0 (00H-7FH) MB = 15 (80H-FFH) MBE = 1 : MB = MBS (MBS = 0, 1, 15) MB = 15, fmem = FB0H-FBFH, FF0H-FFFH MB = 15, pmem = FC0H-FFFH addr = 0000H-1F7FH addr = (Current PC) -15 to (Current PC) - 1 (Current PC) +2 to (Current PC) + 16 caddr = 0000H-0FFFH (PC12 = 0) or 1000H-1F7FH (PC12 = 1) faddr = 0000H-07FFH taddr = 0020H-007FH MB = MBE . MBS (MBS = 0, 1, 4, 5, 6, 7, 15) *12 MBE = 0: MB = 0 (00H-7FH) MB = 15 (80H-FFH) MBE = 1: MB = MBS (MBS = 0, 1, 4, 5, 6, 7, 15) Data memory addressing Program memory addressing Data memory addressing
*4 *5 *6 *7 *8 *9 *10 *11
Remarks 1:
2: 3: 4: 5:
MB indicates memory bank that can be accessed. In *2, MB = 0 regardless of MBE and MBS. In *4 and *5, MB = 15 regardless of MBE and MBS. *6 to *10 indicate areas that can be addressed. When MBS is 4, 5, 6 or 7, addressing area is in the EEPROM area.
(4) Machine cycle field In this field, S indicates the number of machine cycles required when an instruction having a skip function skips. The value of S varies as follows: * When no instruction is skipped .................................................................................. S = 0 * When 1-byte or 2-byte instruction is skipped ........................................................... S = 1 * When 3-byte instruction (BR !addr or CALL !addr) is skipped .............................. S = 2
Note : The GETI instruction is skipped in one machine cycle.
One machine cycle equals to one cycle of the CPU clock , (=tCY), and can be changed in three steps depending on the setting of the processor clock control register (PCC).
41
PD75048
Machine Bytes Cycles 1 2 2 2 2 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 2 2 2 1 2 1 1 1 1 1 1 1 2 1 2 1 2 1 1 2 1 2 2 2 2 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 2 2 2 1 2 3 3 1+S 1+S 1 1+S 1 2 1 2 1 2 1 1 2 A n4 reg1 n4 XA n8 HL n8 rp2 n8 A (HL) A (rpa1) XA (HL) (HL) A (HL) XA A (mem) XA (mem) (mem) A (mem) XA A reg XA rp reg1 A rp1 XA A (HL) A (rpa1) XA (HL) A (mem) XA (mem) A reg1 XA rp XA (PC12-8+DE)ROM XA (PC12-8+XA)ROM A A+n4 A A+(HL) A, CY A+(HL)+CY A A-(HL) A, CY A-(HL)-CY A A n4 A A (HL) A A n4 A A (HL) A A n4 A A (HL) CY A0, A3 CY, An-1 An AA *11 *11 *11 *11 *11 *11 *11 borrow carry carry *11 *2 *11 *12 *12 *11 *2 *11 *11 *11 *12 *12 *12 *12 String effect A String effect B Addressing Area
Instructions
Mnemonics
Operand A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @rpa1 XA, @HL @HL, A @HL, XA A,mem XA, mem mem, A mem, XA A, reg XA, rp reg1, A rp1, XA
Operation
Skip Conditions String effect A
Transfer MOV
XCH
A, @HL A, @rpa1 XA, @HL A, mem XA, mem A, reg1 XA, rp
Table Reference Arithmetic Operation
MOVT ADDS ADDC SUBS SUBC AND OR XOR
XA, @PCDE XA, @PCXA A, #n4 A, @HL A, @HL A, @HL A, @HL A, #n4 A, @HL A, #n4 A, @HL A, #n4 A, @HL A A
Accumu- RORC lator Manipu- NOT lation
42
PD75048
Machine Bytes Cycles 1 2 2 1 2 2 1 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1+S 2+S 2+S 1+S 2+S 2+S 1+S 2+S 1 1 1+S 1 2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2 2 2 2 2 2 2 2 2 Addressing Area *11 *12
Instructions Increment/ Decrement
Mnemonics INCS
Operand reg @HL mem
Operation reg reg+1 (HL) (HL)+1 (mem) (mem)+1 reg reg-1 Skip if reg = n4 Skip if (HL) = n4 Skip if A = (HL) Skip if A = reg CY 1 CY 0 Skip if CY = 1 CY CY
(mem.bit) 1 (fmem.bit) 1
Skip Conditions reg = 0 (HL) = 0 (mem) = 0 reg = FH reg = n4
DECS
reg reg, #n4 @HL, #n4 A, @HL A, reg
Compare SKE
*11 *11
(HL) = n4 A = (HL) A = reg
Carry flag lation Bit Manipulation
SET1 CLR1 NOT1
CY CY CY CY mem.bit fmem.bit pmem.@L @H+mem.bit
Manipu- SKT Memory/ SET1
CY = 1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 (mem.bit) = 1 (fmem.bit) = 1 (pmem.@L) = 1 (@H+mem.bit) = 1 (mem.bit) = 0 (fmem.bit) = 0 (pmem.@L) = 0 (@H+mem.bit) = 0 (fmem.bit) = 1 (pmem.@L) = 1 (@H+mem.bit) = 1
(pmem7-2 + L3-2.bit(L1-0)) 1 (H + mem3-0.bit) 1
(mem.bit) 0 (fmem.bit) 0
CLR1
mem.bit fmem.bit pmem.@L @H+mem.bit
(pmem7-2 + L3-2.bit(L1-0) 0 (H+mem3-0.bit) 0 Skip if(mem.bit) = 1 Skip if(fmem.bit) = 1
Skip if(pmem7-2+L3-2.bit (L1-0)) = 1
SKT
mem.bit fmem.bit pmem.@L @H+mem.bit
Skip if(H + mem3-0.bit) = 1 Skip if(mem.bit) = 0 Skip if(fmem.bit) = 0
Skip if(pmem7-2 +L3-2.bit (L1-0)) = 0
SKF
mem.bit fmem.bit pmem.@L @H+mem.bit
Skip if (H + mem3-0.bit) = 0 Skip if(fmem.bit) = 1 and clear Skip if(pmem7-2+L3-2.bit (L1-0)) = 1 and clear
Skip if (H+mem3-0.bit) = 1 and clear
SKTCLR fmem.bit pmem.@L @H+mem.bit AND1 CY,fmem.bit CY,pmem.@L CY,@H+mem.bit OR1 CY,fmem.bit CY,pmem.@L CY,@H+mem.bit XOR1 CY,fmem.bit CY,pmem.@L CY,@H+mem.bit
CY CY (fmem.bit) CY CY (pmem7-2+L3-2.bit(L1-0)) CY CY (H+mem3-0.bit) CY CY (fmem.bit) CY CY (pmem7-2+L3-2.bit (L1-0)) CY CY (H+mem3-0.bit) CY CY (fmem.bit)
CY CY (pmem7-2+L3-2.bit (L1-0))
CY CY (H+mem3-0.bit)
43
PD75048
Machine Bytes Cycles -- -- Addressing Area *6
Instructions Branch
Mnemonics BR
Operand addr
Operation PC12-0 addr (The most suitable instruction is selectable from among BR !addr, BRCB !caddr, and BR $addr depending on the assembler.) PC12-0 addr PC12-0 addr PC12-0 PC12 + caddr11-0 (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE,0, 0, PC12 PC12-0 addr,SP SP-4 (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE,0, 0, PC12 PC12-0 00,faddr,SP SP-4 MBE,x,x,PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) SP SP+4 MBE,x,x,PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) SP SP+4, then skip unconditionally MBE,x,x,PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) PSW (SP+4)(SP+5), SP SP+6 (SP-1)(SP-2) rp, SP SP-2 (SP-1) MBS,(SP-2) 0,SP SP-2 rp (SP+1)(SP),SP SP+2 MBS (SP+1),SP SP+2 IME 1 IExxx 1 IME 0 IExxx 0 A PORTn XA PORTn+1,PORTn PORTn A PORTn+1,PORTn XA
(n = 0-11) (n = 4, 6) (n = 2-10) (n = 4, 6)
Skip Conditions
!addr $addr BRCB Subrou- CALL tine/ Stack Control CALLF !caddr !addr
3 1 2 3
3 2 2 3
*6 *7 *8 *6
!faddr
2
2
*9
RET
1
3
RETS
1
3+S
Unconditional
RETI
1
3
PUSH POP Interrupt Control I/O DI EI
rp BS rp BS IExxx IExxx
1 2 1 2 2 2 2 2 2 2 2 2 2 2 1
1 2 1 2 2 2 2 2 2 2 2 2 2 2 1 2 3
IN OUT
A,PORTn XA,PORTn PORTn,A PORTn,XA
CPU Control Special
HALT STOP NOP SEL GETI MBn taddr
Set HALT Mode(PCC.2 1) Set STOP Mode (PCC.3 1) No Operation MBS n(n=0, 1, 4, 5, 6, 7, 15) . Where TBR instruction, PC12-0 (taddr)4-0+(taddr+1) . Where TCALL instruction, (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, 0, 0, PC12 PC12-0 (taddr)4-0+(taddr+1) SP SP-4 . Except for TBR and TCALL instructions, Instruction execution of (taddr)(taddr+1) *10
2 1
Depends on referenced instruction
Note : When executing the IN/OUT instruction, MBE = 0, or MBE = 1, and MBS = 15.
5
Remarks : TBR and TCALL instructions are assembler seudo-instructions for the table definition of
GETI instruction. 44
PD75048
11. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Ta = 25C)
Parameter Supply Voltage Input Voltage Symbol VDD VI1 VI2 Other than ports 4, 5, 10 Ports 4, 5, 10 w/pull-up resistor Open drain Output Voltage High-Level Output Current Low-Level Output Current VO IOH IOL* 1 pin All pins Ports 0, 3, 4, 5 1 pin Other than ports 0, 3, 4, 5 1 pin Total of ports 0, 3 - 9, 11 Total of ports 0, 2, 10 Operating Temperature Storage Temperature Topt Tstg Peak rms Peak rms Peak rms Peak rms Conditions Ratings -0.3 to +7.0 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to +11 -0.3 to VDD+0.3 -10 -30 30 15 20 5 170 120 30 20 -10 to +70 -65 to +150 Unit V V V V V mA mA mA mA mA mA mA mA mA mA C C
*: rms = Peak value x Duty Note: Even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. The absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. Be sure not to exceed or fall below this value when using the product. EEPROM RATINGS (Ta = -10 to +70C, VDD = 2.7 to 6.0 V)
Parameter Write Times Data Retention Time Symbol -- -- Conditions 100,000 10 times years
5
CAPACITANCE (Ta = 25C, VDD = 0 V)
Parameter Input Capacitance Output Capacitance Input/Output Symbol CI CO CIO f = 1 MHz Pins other than thosemeasured are at 0 V Conditions MIN. TYP. MAX. 15 15 15 Unit pF pF pF
45
PD75048
MAIN SYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS (Ta = -10 to +70C, VDD = 2.7 to 6.0 V)
Recommended Constants
Oscillator Ceramic
Item Oscillation frequency(fX)* 1
Conditions VDD = oscillation voltage range
MIN. 2.0
TYP.
MAX. 5.0 *3
Unit MHz
X1
X2
C1 VDD
C2
Oscillation stabiliza- After VDD come to MIN. value of tion time* 2 oscillation voltage range
4
ms
Crystal
X1 X2
Oscillation frequency (fX)* 1 Oscillation stabiliza- VDD = 4.5 to 6.0 V tion time* 2
2.0
4.19
5.0
*3
MHz ms ms
10 30
C1 VDD
C2
External Clock
X1 X2
X1 input frequency (fX)*1 X1 input high-, low-level widths (tXH, tXL)
2.0
5.0
*3
MHz
100
250
ns
mPD74HCU04
*1: Only to express the characteristics of the oscillator circuit. For instruction execution time, refer to AC Characteristics. 2: Time required for oscillation to stabilize after VDD has reached the minimum volue of the oscillation voltage range or the STOP mode has been released. 3: When the oscillation frequency is 4.19 MHz < fx 5.0 MHz, do not select PCC = 0011 as the instruction execution time: otherwise, one machine cycle is set to less than 0.95 s, falling short of the rated minimum value of 0.95 s. 5 Note: When using the oscillation circuit of the main system clock, wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity: * Keep the wiring length as short as possible. * Do not cross the wiring over the other signal lines. * Do not route the wiring in the vicinity of lines through which a high alternating current flows. * Always keep the ground point of the capacitor of the oscillator circuit at the same potential as VDD. Do not connect the ground pattern through which a high curent flows. * Do not extract signals from the oscillation circuit.
46
PD75048
SUBSYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS (Ta = -10 to +70C, VDD = 2.7 to 6.0 V)
Recommended Constants
XT1 XT2 R C3 VDD C4
Oscillator Crystal
Item Oscillation frequency (fXT)* 1
Conditions
MIN. 32
TYP. 32.768 1.0
MAX. 35 2 10
Unit kHz ms ms
Oscillation stabiliza- VDD = 4.5 to 6.0 V tion time*2
External Clock
XT1 XT2
XT1 input frequency (fXT)*1 XT1 input high-, low-level widths (tXTH, tXTL)
32
100
kHz
5
15
s
*1: Indicates only the characteristics of the oscillator circuit. For instruction execution time, refer to AC Characteristics. 2: Time required for oscillation to stabilize after VDD has reached the minimum value of the oscillation voltage range. Note: When using the oscillation circuit of the subsystem clock, wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity: * Keep the wiring length as short as possible. * Do not cross the wiring over the other signal lines. * Do not route the wiring in the vicinity of lines through which a high alternating current flows. * Always keep the ground point of the capacitor of the oscillator circuit at the same potential as VDD. Do not connect the ground pattern through which a high current flows. * Do not extract signals from the oscillation circuit. The amplification factor of the subsystem clock oscillation circuit is designed to be low to reduce the current dissipation and therefore, the subsystem clock oscillation circuit is influenced by noise more easily than the main system clock oscillation circuit. When using the subsystem clock, therefore, exercise utmost care in wiring the circuit. 5
47
PD75048
DC CHARACTERISTICS (Ta = -10 to +70C, VDD = 2.7 to 6.0 V)
Parameter High-Level Input Voltage Symbol VIH1 VIH2 VIH3 VIH4 Low-level Input Voltage VIL1 VIL2 VIL3 High-Level Output Voltage Low-Level Output Voltage VOH VOL Conditions Ports 2,3,8,9,11 Ports 0,1,6,7, RESET Ports 4,5,10 X1, X2, XT1, XT2 Ports 2-5, 8-11 Ports 0, 1, 6, 7, RESET X1, X2, XT1, XT2 VDD = 4.5 to 6.0V, IOH = -1 mA IOH = -100 A Ports 3,4,5 VDD = 4.5 to 6.0V, IOL = 15mA w/pull-up resistor Open-drain MIN. 0.7VDD 0.8VDD 0.7VDD 0.7VDD VDD-0.5 0 0 0 VDD-1.0 VDD-0.5 0.4 2.0 0.4 0.5 Open-drain pull-up resistor 1 k Other than below X1,X2,XT1 VI = 9V VI = 0V VO = VDD VO = 9V VO = 0V Ports 0,1,2,3,6,7,8 VDD = 5.0V10% (except P00) VI = 0V VDD = 3.0V10% Ports 4,5,10 VO = VDD-2.0 V Port 9 VIN = VDD VDD = 5.0V10% VDD = 3.0V10% VDD = 5.0V10% VDD = 3.0V10% 15 30 15 10 15 10 40 40 40 Ports 4,5,10 (open-drain) Other than below X1,X2,XT1 Other than below Ports 4,5,10 (open-drain) 0.2VDD 3 20 20 -3 -20 3 20 -3 80 300 70 60 70 60 TYP. MAX. VDD VDD VDD 10 VDD 0.3VDD 0.2VDD 0.4 Unit V V V V V V V V V V V V V V
VDD = 4.5 to 6.0V, IOL = 1.6 mA IOL = 400 A SB0, 1 High-Level Input Leakage Current ILIH1 ILIH2 ILIH3 Low-Level Input Leakage Current High-Level Output Leakage Current Low-Level Output Leakage Current ILIL1 ILIL2 ILOH1 ILOH2 ILOL VI = VDD
A A A A A A A A
k k k k k k
Internal Pull-Up Resistor RU1 RU2 Internal Pull-Down Resistor RD
48
PD75048
Parameter
Symbol 4.19MHz crystal oscillator IDD2 IDD3 IDD4 IDD5 XT1 = 0V STOP mode IDD6 C1 = C2 = 22pF
Conditions VDD = 5V10%*2 VDD = 3V10%*3 HALT mode Operation mode HALT mode VDD = 5V10% VDD = 3V10% Ta = 25C 32.768kHz oscillator VDD = STOP mode 3V10%*5 VDD = 5V10% VDD = 3V10% 32.768kHz*4 crystal oscillator VDD = 3V10% VDD = 3V10%
MIN.
TYP. 3.5 0.65 800 350 70 20 0.5 0.3
MAX. 10 1.8 2400 1000 210 60 20 10 5
Unit mA mA
Supply Current *1 IDD1
A A A A A A A A
6
20
*1: Current flowing through internal pull-up resistor. Current flowing when EEPROM is accessed is not included. 2: When PD75048 operates in high-speed mode with processor clock control register (PCC) set to 0011. 3: When PD75048 operates in low-speed mode with PCC set to 0000. 4: When the system clock control register (SCC) is set to 1001, the oscillation of the main system clock is stopped, and the subsystem clock is used. 5: When STOP instruction is executed with SCC set to 0000. Note: Supply current when EEPROM is accessed is shown in EEPROM Characteristics.
49
PD75048
AC CHARACTERISTICS (Ta = -10 to +70C, VDD = 2.7 to 6.0 V)
Parameter CPU Clock Cycle Time (Minimum Instruction Execution Time = 1 Machine Cycle)*1 TI0 Input Frequency TI0 Input High-, LowLevel Widths Interrupt Input High-, Low-Level Widths Symbol tCY Conditions w/main system clock w/subsystem clock fTI tTIH, tTIL tINTH, tINTL VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V INT0 INT1, 2, 4 KR0-7 RESET Low-Level Width tRSL VDD = 4.5-6.0V MIN. 0.95 3.8 114 0 0 0.48 1.8 *2 10 10 10 122 TYP. MAX. 32 32 125 1 275 Unit
s s s
MHz kHz
s s s s s s
*1: The CPU clock () cycle time is determined by the oscillation frequency of the connected oscillator, system clock control register (SCC), and processor clock control register (PCC). The figure on the right is cycle time tCY vs. supply voltage VDD characteristics at the main system clock. *2: 2tCY or 128/fX depending on the setting of the interrupt mode register (IM0).
m Cycle time tCY [[s] s]
6 5 4 3 Operation guaranteed range 32 tCY vs VDD (with main system clock)
2
1
0.5 0 1 2 3 4 5 6 Supply voltage VDD [V]
50
PD75048
SERIAL TRANSFER OPERATION Two-Line and Three-Line Serial I/O Modes (SCK: internal clock output)
Parameter SCK Cycle Time SCK High-, Low-Level Widths
SI Set-Up Time (vs. SCK ) SI Hold Time (vs. SCK )
Symbol tKCY1 tKL1 tKH1 tSIK1 tKSI1 tKSO1
Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V
MIN. 1600 3800 tKCY1/2-50 tKCY1/2-150 150 400
TYP.
MAX.
Unit ns ns ns ns ns ns
SCK SO Output Delay Time
RL = 1k, CL = 100pF*
VDD = 4.5 to 6.0V
250 1000
ns ns
TWO-LINE AND THREE-LINE SERIAL I/O MODES (SCK: external clock input)
Parameter SCK Cycle Time SCK High-, Low-Level Widths
SI Set-Up Time (vs. SCK )
Symbol tKCY2 tKL2 tKH2 tSIK2 tKSI2 tKSO2
Conditions VDD = 4.5 to 6.0V VDD = 4.5 to 6.0V
MIN. 800 3200 400 1600 100 400
TYP.
MAX.
Unit ns ns ns ns ns ns
SI Hold Time (vs. SCK ) SCK SO Output Delay Time
RL = 1k, CL = 100 pF*
VDD = 4.5 to 6.0V
300 1000
ns ns
*: RL and CL are load resistance and load capacitance of the SO output line.
51
PD75048
SBI MODE (SCK: internal clock output (master))
Parameter SCK Cycle Time SCK High-, Low-Level Widths SB0, 1 Set-Up Time (vs. SCK ) SB0, 1 Hold Time (vs. SCK ) SCK SB0, 1 Output Delay Time SCK SB0, 1 SB0,1 SCK SB0, 1 Low-Level Width SB0, 1 High-Level Width Symbol tKCY3 tKL3 tKH3 tSIK3 tKSI3 tKSO3 tKSB tSBK tSBL tSBH
RL = 1k, CL = 100pF*
Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V
MIN. 1600 3800 tKCY3/2-50 tKCY3/2-150 150 tKCY3/2
TYP.
MAX.
Unit ns ns ns ns ns ns
VDD = 4.5 to 6.0V
0 0 tKCY3 tKCY3 tKCY3 tKCY3
250 1000
ns ns ns ns ns ns
SBI MODE (SCK: external clock input (slave))
Parameter SCK Cycle Time SCK Ligh-, Low-Level Widths SB0, 1 Set-Up Time (vs. SCK ) SB0, 1 Hold Time (vs. SCK ) SCK SB0, 1 Output Delay Time SCK SB0, 1 SB0,1 SCK SB0, 1 Low-Level Width SB0, 1 High-Level Width Symbol tKCY4 tKL4 tKH4 tSIK4 tKSI4 tKSO4 tKSB tSBK tSBL tSBH
RL = 1k, CL = 100pF*
Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V
MIN. 800 3200 400 1600 100 tKCY4/2
TYP.
MAX.
Unit ns ns ns ns ns ns
VDD = 4.5 to 6.0V
0 0 tKCY4 tKCY4 tKCY4 tKCY4
300 1000
ns ns ns ns ns ns
*: RL and CL are load resistance and load capacitance of the SB0 and SB1 output lines.
52
PD75048
A/D CONVERTER (Ta = -10 to +70C, VDD = 2.7 to 6.0V, AVSS = VSS = 0V)
Parameter Resolution Absolute Accuracy* 1 Conversion Time*2 Sampling Time*3 Analog Input Voltage Analog Supply Voltage Reference Input Voltage Reference Input Voltage Analog Input Impedance AVREF Current tCONV tSAMP VIAN AVDD AVREF+ AVREFRAN AIREF
1 - LSB) 2
Symbol
Conditions 2.5V AVREF VDD
MIN. 8
TYP. 8
MAX. 8 1.5 168/fX 44/fX
Unit bit LSB
s s
V V V V M mA
AVREF2.5 2.5V (AVref+) - (AVref-) 2.5V (AVref+) - (AVref-) 2.5 0 1000 0.25
AVREF+ VDD AVDD 1.0 2.0
*1: Absolute accuracy excluding quantization error ( = 4.19 MHz)
2: Time since execution of conversion start instruction until end of conversion (EOC = 1) (40.1 s: fX 3: Time since execution of conversion start instruction until end of sampling (10.5 s: fX = 4.19 MHz)
53
PD75048
AC TIMING TEST POINT (excluding X1 and XT1 inputs)
0.8 VDD Test points 0.2 VDD 0.2 VDD 0.8 VDD
CLOCK TIMING
1/fX tXL tXH
X1 input
VDD -0.5V 0.4 V
1/fXT tXTL tXTH
XT1 input
VDD -0.5V 0.4 V
TI0 TIMING
1/fTI tTIL tTIH
TI0
54
PD75048
SERIAL TRANSFER TIMING THREE-LINE SERIAL I/O MODE:
tKCY1 tKL1 tKH1
SCK
tSIK1
tKSI1
SI
Input data
tKS01
SO
Output data
TWO-LINE SERIAL I/O MODE:
tKCY2 tKL2 tKH2
SCK
tSIK2
tKSI2
SB0,1
tKSO2
55
PD75048
SERIAL TRANSFER TIMING BUS RELEASE SIGNAL TRANSFER:
tKCY3,4 tKL3,4 SCK tSIK3,4 tKH3,4
tKSB
tSBL
tSBH
tSBK
tKSI3,4
SB0,1
tKS03,4
COMMAND SIGNAL TRANSFER:
tKCY3,4 tKL3,4 SCK tSIK3,4 tKH3,4
tKSB
tSBK
tKSI3,4
SB0,1
tKS03,4
INTERRUPT INPUT TIMING
tINTL tINTH
INT0, 1, 2, 4 KR0-7
RESET INPUT TIMING
tRSL
RESET
56
PD75048
EEPROM CHARACTERISTICS
Parameter Supply current for EEPROM access*1 Symbol IDD7 Conditions 4.19MHz crystal oscillator VDD = C1 = C = 22pF VDD = 3V+10%*3 5V+10%*2 MIN. TYP. 6.5 2 MAX. 20 6 Unit mA mA
*1: Current flowing through the internal pull-up resistor is not included. 2: When the processor clock control register (PCC) is set to 0011 and the high-speed mode is used. 3: When PCC is set to 0000 and the low-speed mode is used. EEPROM WRITE TIME Select the write time of the EEPROM in accordance with the oscillation frequency of the main system clock as follows:
Oscillation Frequency of Main System Clock (fX) fX = 2.0 to 5.0 MHz fX = 2.0 to 4.2 MHz fX = 2.0 MHz Setting of EEPROM Control Register EWTC1 0 0 1 EWTC0 0 1 0
Write time 212 x 18/fX (17.6 ms) 211 x 18/fX (8.8 ms) 210 x 18/fX
Remarks: ( ): fX = 4.19 MHz
LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE (Ta = -10 to +70C)
Parameter Data Retention Supply Voltage Data Retention Supply Current*1 Release Signal Set Time Oscillation Stabilization Wait Time*2 Symbol VDDDR IDDDR tSREL tWAIT Released by RESET Released by interrupt request VDDDR = 2.0 V 0 2 17/fX
*3
Conditions
MIN. 2.0
TYP.
MAX. 6.0
Unit V
0.1
10
A s
ms ms
*1: Does not include current flowing through internal pull-up resistor 2: The oscillation stabilization wait time is the time during which the CPU is stopped to prevent unstable operation when oscillation is started. 3: Depends on the setting of the basic interval timer mode register (BTM) as follows:
BTM3 - - - - BTM2 0 0 1 1 BTM1 0 1 0 1 BTM0 0 1 1 1 WAIT time ( ): fX = 4.19 MHz 220/fX (approx. 250 ms) 217/fX (approx. 31.3 ms) 215/fX (approx. 7.82 ms) 213/fX (approx. 1.95 ms)
57
PD75048
DATA RETENTION TIMING (releasing STOP mode by RESET)
Internal reset operation HALT mode STOP mode Data retention mode Operation mode
VDD VDDDR STOP instruction execution RESET tSREL
tWAIT
DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt)
HALT mode STOP mode Data retention mode Operation mode
VDD VDDDR STOP instruction execution Standby release signal (interrupt request) tSREL
tWAIT
58
PD75048
12. PERFORMANCE CURVE
IDD vs VDD (Crystal oscillation) 10 (T a = 25 C)
5.0
High-speed mode PCC = 0011 Medium-speed mode PCC = 0010 Low-speed mode PCC = 0000
1.0
Main system clock HALT mode
0.5
Subsystem clock Operation mode
Supply current IDD (mA)
0.1
With main system clock stopped Subsystem clock HALT mode
0.05
Main system clock STOP mode Subsystem clock oscillation
0.01
X1
X2 Crystal
XT1 Crystal
XT2 330 k
0.005
4.19 MHz
32.768 kHz
22 pF
22 pF
22 pF
22 pF
VDD
VDD
0.001
0
1
2
3
4
5
6
7
Supply voltage VDD (V)
59
PD75048
IDD vs VDD (Crystal oscillation) 10
(T a = 25 C)
5.0
High-speed mode PCC = 0011 Medium-speed mode PCC = 0010 Low-speed mode PCC = 0000
1.0
Main system clock HALT mode
0.5
Subsystem clock Operation mode
Supply current IDD (mA)
0.1
With main system clock stopped Subsystem clock HALT mode
0.05
Main system clock STOP mode Subsystem clock oscillation
0.01
X1
X2 Crystal 2.0 MHz
XT1 Crystal
XT2 330 k
0.005
32.768 kHz
22 pF
22 pF
22 pF
22 pF
VDD
VDD
0.001
0
1
2
3
4
5
6
7
Supply voltage VDD (V)
60
PD75048
13. PACKAGE DRAWINGS
64 PIN PLASTIC SHRINK DIP (750 mil)
64 33
1 A
32
K L
J I
F D
G
H
N
M
C
B
M
R
NOTE 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel.
ITEM MILLIMETERS A B C D F G H I J K L M N R 58.68 MAX. 1.78 MAX. 1.778 (T.P.) 0.500.10 0.9 MIN. 3.20.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 19.05 (T.P.) 17.0 0.25 +0.10 -0.05 0.17 0~15
INCHES 2.311 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.035 MIN. 0.1260.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.750 (T.P.) 0.669 0.010 +0.004 -0.003 0.007 0~15 P64C-70-750A,C-1
61
PD75048
64 PIN PLASTIC QFP (
14)
A B
48 49
33 32 detail of lead end
C
D
S
64 1
17 16
F
G
H
IM
J
K
P
N
L P64GC-80-AB8-3 ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 17.6 0.4 14.0 0.2 14.0 0.2 17.6 0.4 1.0 1.0 0.35 0.10 0.15 0.8 (T.P.) 1.8 0.2 0.8 0.2 0.15+0.10 -0.05 0.10 2.55 0.1 0.1 2.85 MAX. INCHES 0.693 0.016 0.551+0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.039 0.039 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.071 0.008 0.031+0.009 -0.008 0.006+0.004 -0.003 0.004 0.100 0.004 0.004 0.112 MAX.
NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
62
M
55
Q
PD75048
14. RECOMMENDED SOLDERING CONDITIONS
It is recommended that PD75048 be soldered under the following conditions. For details on the recommended soldering conditions, refer to Information Document "Semiconductor Devices Mounting Manual" (IEI-616). For other soldering methods and conditions, consult NEC.
Table 14-1 Soldering Conditions of Surface Mount Type
PD75048GC - xxx - AB8: 64-pin plastic QFP (
Soldering Method Ware Soldering
14 mm)
Symbol for Recommended Condition
Soldering Conditions Soldering bath temperature: 260C max., time: 10 seconds max., number of times: 1, maximum number of days: 2 days*, (beyond this period, 16 hours of pre-baking is required at 125C), Pre-heating temperature: 120C max. Package peak temperature: 230C, time: 30 seconds max. (210C min.), number of times: 1, maximum number of days: 2 days* (beyond this period, 16 hours of pre-baking is required at 125C) Package peak temperature: 215C, time: 40 seconds max. (200C min.), number of times: 1, maximum number of days: 2 days* (beyond this period, 16 hours of pre-baking is required at 125C) Pin temperature: 300C max., time: 3 seconds max. (per side)
WS60-162-1
Infrared Reflow
IR30-162-1
VPS
VP15-162-1
Pin Partial Heating
--
*:
Number of days after unpacking the dry pack. Storage conditions are 25C and 65%RH max. Do not use two or more soldering methods in combination (except the pin partial heating method).
Note:
Table 14-2 Soldering Conditions of Through-Hole Type
PD75048CW - xxx: 64-pin plastic shrink DIP (750 mil)
Soldering Method Wave soldering (lead parts only) Pin Partial Heating Soldering Conditions Soldering bath temperature: 260C max., time: 10 seconds max., Pin temperature: 260oC max., time: 10 seconds max.
Caution:
The wave soldering must be performed at the lead part only. Note that the soldering must not be directly contacted to the board.
Notice
A model that can be soldered under the more stringent conditions (infrared reflow peak temperature: 235C, numbver of times:2, and an extended number of days) is also available. For details, consult NEC.
63
PD75048
APPENDIX A. DIFFERENCES BETWEEN PD75048 AND 75028/75008 FUNCTIONS
Item ROM (bytes) RAM (x4 bits) EEPROM (x4 bits) Cycle I/O Port Subsystem Clock CMOS Input CMOS I/O N-ch OpenDrain I/O A/D Converter 16-bit Multifunction Timer 1 ch 1024 122s (32.768 kHz) 12 * Pull-up via software: 27 (except P00) 48 24 * Pull-down via software: 4 12 (10 V, pull-up by mask option) * 8-bit resolution x 8 channels * Low-voltage operation: VDD = 2.7 - 6.0 * * * * 8-bit timer mode PWM output mode 16-bit free running timer mode 16-bit integral A/D converter mode External: 3, Internal: 4 External: 1, Internal: 1 2 kHz, 4 kHz, 32 kHz (at 4.19 MHz, 32.768 kHz operation) 2 kHz (at 4.19 MHz, 32.768 kHz operation) * 64-pin plastic shrink DIP (750 mil) * 64-pin plastic QFP ( Supply Voltage Operating Temperature PROM Model -10 to +70C 14 mm) VDD = 2.7 - 6.0 V -40 to +70C -40 to +85C * 42-pin plastic shrink DIP (600 mil) * 44-pin plastic QFP ( 10 mm) 8 Pull-up via software 34 18 (except P00) 8 (10 V, pull-up by mask option) None Instruction Main System Clock 0.95 s, 1.91 s, 15.3 s (4.19 MHz)
PD75048
PD75028
8064 512 None
PD75008
None
Vector Interrupt Test Input Buzzer Output (BUZ) Package
External: 3, Internal: 6
External: 3, Internal: 3
5
PD75P048
PD75P036
PD75P008
64
PD75048
APPENDIX B. DEVELOPMENT TOOLS
The following development tools are readily available to support development of systems using
PD75048:
Hardware IE-75000-R*1 IE-75001-R IE-75000-R-EM*2 EP-75028CW-R EP-75028GC-R EV-9200GC-64 PG-1500 PA-75P036GC Emulation board for IE-75000-R and IE-75001-R Emulation prove for PD75048 Emulation prove for PD75048, provided with EV-9200GC-64, 64-pin conversion socket PROM programmer
PROM programmer adapter solely used for PD75P048GC. It is connected to PG-1500.
In-circuit emulator for 75X series
PA-75P036CW
PROM programmer adapter solely used for PD75P048CW. It is connected to PG-1500.
Software
IE Control Program Host machine PG-1500 Controller RA75X Relocatable Assembler PC-9800 series (MS-DOSTM Ver. 3.30 to Ver. 5.00A*3) IBM PC/ATTM (PC DOS TM Ver. 3.1)
*1: Maintenance product 2: Not provided with IE-75001-R. 3: Ver. 5.00/5.00A has a task swap function, but this function cannot be used with this software.
Remarks : For development tools from other companies, refer to 75X Series Selection Guide (IF151).
65
PD75048
[MEMO]
66
PD75048
GENERAL NOTES ON CMOS DEVICES
STATIC ELECTRICITY (ALL MOS DEVICES)
Exercise care so that MOS devices are not adversely influenced by static electricity while being
handled. The insulation of the gates of the MOS device may be destroyed by a strong static charge. Therefore, when transporting or storing the MOS device, use a conductive tray, magazine case, or conductive buffer materials, or the metal case NEC uses for packaging and shipment, and use grounding when assembling the MOS device system. Do not leave the MOS device on a plastic plate and do not touch the pins of the device. Handle boards on which MOS devices are mounted similarly .
PROCESSING OF UNUSED PINS (CMOS DEVICES ONLY)
Fix the input level of CMOS devices. Unlike bipolar or NMOS devices, if a CMOS device is operated with nothing connected to its
input pin, intermediate level input may be generated due to noise, and an inrush current may flow through the device, causing the device to malfunction. Therefore, fix the input level of the device by using a pull-down or pull-up resistor. If there is a possibility that an unused pin serves as an output pin (whose timing is not specified), each pin should be connected to VDD or GND through a resistor. Refer to "Processing of Unused Pins" in the documents of each devices.
STATUS BEFORE INITIALIZATION (ALL MOS DEVICES)
The initial status of MOS devices is undefined upon power application. Since the characteristics of an MOS device are determined by the quantity of injection at the
molecular level, the initial status of the device is not controlled during the production process. The output status of pins, I/O setting, and register contents upon power application are not guaranteed. However, the items defined for reset operation and mode setting are subject to guarantee after the respective operations have been executed. When using a device with a reset function, be sure to reset the device after power application.
67
PD75048
[MEMO]
NEC is manufacturing and selling the products under microcomputer (with on-chip EEPROM) patent license with the BULL CP8. This product should not be used for IC cards (SMART CARD).
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties b y or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for uses in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for the applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation
Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime system, etc. M4 92.6
MS-DOS is a trademark of Microsoft Corporation. PC DOS and PC/AT are trademarks of IBM Corporation.
68

▲Up To Search▲

Price & Availability of UPD75048GC

	To Download UPD75048GC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .